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vafile.cpp
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1 /***************************************************************************
2  vafile.cpp
3  ------------
4  begin : Sun Oct 26 2009
5  copyright : (C) 2009 by Stefan Jahn
6  email : stefa@lkcc.org
7  ***************************************************************************/
8 
9 /***************************************************************************
10  * *
11  * This program is free software; you can redistribute it and/or modify *
12  * it under the terms of the GNU General Public License as published by *
13  * the Free Software Foundation; either version 2 of the License, or *
14  * (at your option) any later version. *
15  * *
16  ***************************************************************************/
17 
18 #include <qstring.h>
19 #include <qregexp.h>
20 #include <qfile.h>
21 #include <qfileinfo.h>
22 
23 #include "vafile.h"
24 
25 // -------------------------------------------------------
27  ModuleName = "";
28  PortNames = "";
29 }
30 
31 // -------------------------------------------------------
33 {
34  if (isfile) {
35  QFile f (File);
36  if (!f.open (IO_ReadOnly))
37  File = "";
38  else {
39  QByteArray FileContent = f.readAll ();
40  File = QString (FileContent);
41  }
42  f.close();
43  }
44 
45  QString s;
46  int i=0, j, k=0;
47  while((i=File.find("//", i)) >= 0) { // remove all Verilog-A comments
48  j = File.find('\n', i+2); // (This also finds "//" within a ...
49  if(j < 0) // string, but as no strings are ...
50  File = File.left(i); // allowed in module headers, it ...
51  else // does not matter.)
52  File.remove(i, j-i);
53  }
54 
55  i=0;
56  while((i=File.find("/*", i)) >= 0) { // remove all Verilog-A comments
57  j = File.find("*/", i+2); // (This also finds "/*" within a ...
58  if(j < 0) // string, but as no strings are ...
59  File = File.left(i); // allowed in module headers, it ...
60  else // does not matter.)
61  File.remove(i, j-i+2);
62  }
63 
64  QRegExp Expr,Expr1;
65  Expr.setCaseSensitive(true);
66  Expr1.setCaseSensitive(true);
67  k--;
68  Expr.setPattern("\\bmodule\\b"); // start of last module
69  k = File.findRev(Expr, k);
70  if(k < 0)
71  return;
72 
73  Expr.setPattern("\\bendmodule\\b"); // end of last module
74  i = File.find(Expr, k+7);
75  if(i < 0)
76  return;
77  s = File.mid(k+7, i-k-7); // cut out module declaration
78 
79  Expr.setPattern("\\b");
80  i = s.find(Expr);
81  if(i < 0)
82  return;
83  j = s.find(Expr, i+1);
84  if(j < 0)
85  return;
86  ModuleName = s.mid(i, j-i); // save module name
87 
88  i = s.find('(', j);
89  if(i < 0)
90  return;
91 
92  j = s.find(')', i);
93  if(j < 0)
94  return;
95  s = s.mid(i+1, j-i-1);
96 
97  // parse ports, i.e. network connections
98  PortNames = parsePorts (s, 0);
99 }
100 
101 // -------------------------------------------------------
102 QString VerilogA_File_Info::parsePorts(QString s, int i)
103 {
104  QRegExp Expr,Expr1;
105  Expr.setCaseSensitive(true);
106  Expr1.setCaseSensitive(true);
107 
108  int j;
109  i = 0; // remove all Verilog-A identifiers (e.g. "input")
110  Expr.setPattern("(\\binput\\b|\\boutput\\b|\\binout\\b)");
111  Expr1.setPattern("(\\b)");
112  while((i=s.find(Expr, i)) >= 0) {
113  j = s.find(Expr1, i+1);
114  if(j < 0)
115  s = s.left(i);
116  else
117  s.remove(i, j-i);
118  }
119 
120  s.remove(' ');
121  s.remove('\n');
122  s.remove('\t');
123  return s;
124 }