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fa1b.cpp
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1 /***************************************************************************
2  fa1b
3  ------
4  begin : December 2008
5  copyright : (C) 2008 by Mike Brinson
6  email : mbrin72043@yahoo.co.uk
7  ***************************************************************************/
8 
9 /*
10  * fa1b.cpp - device implementations for fa1b module
11  *
12  * This is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation; either version 2, or (at your option)
15  * any later version.
16  *
17  */
18 
19 #include "fa1b.h"
20 #include "node.h"
21 #include "main.h"
22 
23 fa1b::fa1b()
24 {
25  Type = isComponent; // Analogue and digital component.
26  Description = QObject::tr ("1bit full adder verilog device");
27 
28  Props.append (new Property ("TR", "6", false,
29  QObject::tr ("transfer function high scaling factor")));
30  Props.append (new Property ("Delay", "1 ns", false,
31  QObject::tr ("output delay")
32  +" ("+QObject::tr ("s")+")"));
33 
34  createSymbol ();
35  tx = x1 + 19;
36  ty = y2 + 4;
37  Model = "fa1b";
38  Name = "Y";
39 }
40 
42 {
43  fa1b * p = new fa1b();
44  p->Props.getFirst()->Value = Props.getFirst()->Value;
45  p->recreate(0);
46  return p;
47 }
48 
49 Element * fa1b::info(QString& Name, char * &BitmapFile, bool getNewOne)
50 {
51  Name = QObject::tr("1Bit FullAdder");
52  BitmapFile = (char *) "fa1b";
53 
54  if(getNewOne) return new fa1b();
55  return 0;
56 }
57 
59 {
60  Lines.append(new Line(-30, -40, 30,-40,QPen(QPen::darkBlue,2)));
61  Lines.append(new Line( 30, -40, 30, 50,QPen(QPen::darkBlue,2)));
62  Lines.append(new Line( 30, 50,-30, 50,QPen(QPen::darkBlue,2)));
63  Lines.append(new Line(-30, 50,-30,-40,QPen(QPen::darkBlue,2)));
64 
65  Lines.append(new Line(-50,-10,-30,-10,QPen(QPen::darkBlue,2))); // A
66  Lines.append(new Line(-50, 10,-30, 10,QPen(QPen::darkBlue,2))); // B
67  Lines.append(new Line(-50, 30,-30, 30,QPen(QPen::darkBlue,2))); // CI
68  Lines.append(new Line( 30, 10, 50, 10,QPen(QPen::darkBlue,2))); // CO
69  Lines.append(new Line( 30,-10, 50,-10,QPen(QPen::darkBlue,2))); // S
70 
71  Texts.append(new Text(-25, 17, "CI", QPen::darkBlue, 12.0));
72  Texts.append(new Text( 0, -3, "CO", QPen::darkBlue, 12.0));
73 
74  Lines.append(new Line(-10,-35, 10, -35, QPen(QPen::darkBlue,2)));
75  Lines.append(new Line(-10,-35, 5, -25, QPen(QPen::darkBlue,2)));
76  Lines.append(new Line( 5,-25,-10, -15, QPen(QPen::darkBlue,2)));
77  Lines.append(new Line(-10,-15, 10, -15, QPen(QPen::darkBlue,2)));
78 
79  Ports.append(new Port(-50,-10)); // A
80  Ports.append(new Port(-50, 10)); // B
81  Ports.append(new Port(-50, 30)); // CI
82  Ports.append(new Port( 50, 10)); // CO
83  Ports.append(new Port( 50,-10)); // S
84 
85  x1 = -50; y1 = -44;
86  x2 = 50; y2 = 54;
87 }
88 
89 QString fa1b::vhdlCode( int )
90 {
91  QString s="";
92 
93  QString td = Props.at(1)->Value; // delay time
94  if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
95  td += ";\n";
96 
97  QString A = Ports.at(0)->Connection->Name;
98  QString B = Ports.at(1)->Connection->Name;
99  QString CI = Ports.at(2)->Connection->Name;
100  QString CO = Ports.at(3)->Connection->Name;
101  QString S = Ports.at(4)->Connection->Name;
102 
103  s = "\n " + Name + ":process (" + A + ", " + B + ", " + CI + ")\n" +
104  " begin\n" +
105  " " + CO + " <= (" + A + " and " + B + ") or (" + CI + " and (" + A + " xor " + B + "))" + td +
106  " " + S + " <= " + CI + " xor " + A + " xor " + B + td +
107  " end process;\n";
108  return s;
109 }
110 
111 QString fa1b::verilogCode( int )
112 {
113  QString td = Props.at(1)->Value; // delay time
114  if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
115 
116  QString l = "";
117 
118  QString A = Ports.at(0)->Connection->Name;
119  QString B = Ports.at(1)->Connection->Name;
120  QString CI = Ports.at(2)->Connection->Name;
121  QString CO = Ports.at(3)->Connection->Name;
122  QString S = Ports.at(4)->Connection->Name;
123 
124  QString COR = "CO_reg" + Name + CO;
125  QString SR = "S_reg" + Name + S;
126 
127  l = "\n // " + Name + " 1bit fulladder\n" +
128  " assign " + CO + " = " + COR + ";\n" +
129  " reg " + COR + " = 0;\n" +
130  " assign " + S + " = " + SR + ";\n" +
131  " reg " + SR + " = 0;\n" +
132  " always @ ("+ A + " or " + B + " or " + CI + ")\n" +
133  " begin\n" +
134  " " + COR + " <=" + td + " (" + A + " && " + B + ") || " + CI + " && " + "(" + A + " ^ " + B + ");\n" +
135  " " + SR + " <=" + td + " (" + CI + " ^ " + A + " ^ " + B + ");\n" +
136  " end\n";
137 
138  return l;
139 }
140