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dff_SR.cpp
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1 /***************************************************************************
2  dff_SR
3  --------
4  begin : December 2008
5  copyright : (C) 2008 by Mike Brinson
6  email : mbrin72043@yahoo.co.uk
7  ***************************************************************************/
8 
9 /*
10  * dff_SR.cpp - device implementations for dff_SR module
11  *
12  * This is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation; either version 2, or (at your option)
15  * any later version.
16  *
17  */
18 
19 #include "dff_SR.h"
20 #include "node.h"
21 #include "main.h"
22 
23 dff_SR::dff_SR()
24 {
25  Type = isComponent; // Analogue and digital component.
26  Description = QObject::tr ("D flip flop with set and reset verilog device");
27 
28  Props.append (new Property ("TR_H", "6", false,
29  QObject::tr ("cross coupled gate transfer function high scaling factor")));
30  Props.append (new Property ("TR_L", "5", false,
31  QObject::tr ("cross coupled gate transfer function low scaling factor")));
32  Props.append (new Property ("Delay", "1 ns", false,
33  QObject::tr ("cross coupled gate delay")
34  +" ("+QObject::tr ("s")+")"));
35 
36  createSymbol ();
37  tx = x1 + 4;
38  ty = y2 + 4;
39  Model = "dff_SR";
40  Name = "Y";
41 }
42 
43 Component * dff_SR::newOne()
44 {
45  dff_SR * p = new dff_SR();
46  p->Props.getFirst()->Value = Props.getFirst()->Value;
47  p->recreate(0);
48  return p;
49 }
50 
51 Element * dff_SR::info(QString& Name, char * &BitmapFile, bool getNewOne)
52 {
53  Name = QObject::tr("D-FlipFlop w/ SR");
54  BitmapFile = (char *) "dff_SR";
55 
56  if(getNewOne) return new dff_SR();
57  return 0;
58 }
59 
60 void dff_SR::createSymbol()
61 {
62  // put in here symbol drawing code and terminal definitions
63  Lines.append(new Line(-30,-40, 30,-40,QPen(QPen::darkBlue,2)));
64  Lines.append(new Line( 30,-40, 30, 40,QPen(QPen::darkBlue,2)));
65  Lines.append(new Line( 30, 40,-30, 40,QPen(QPen::darkBlue,2)));
66  Lines.append(new Line(-30, 40,-30,-40,QPen(QPen::darkBlue,2)));
67 
68  Lines.append(new Line(-50,-20,-30,-20,QPen(QPen::darkBlue,2)));
69  Lines.append(new Line(-50, 20,-30, 20,QPen(QPen::darkBlue,2)));
70  Lines.append(new Line( 30, 20, 50, 20,QPen(QPen::darkBlue,2)));
71  Lines.append(new Line( 30,-20, 50,-20,QPen(QPen::darkBlue,2)));
72 
73  Lines.append(new Line( -30, 10,-20, 20,QPen(QPen::darkBlue,2)));
74  Lines.append(new Line( -30, 30,-20, 20,QPen(QPen::darkBlue,2)));
75 
76  Lines.append(new Line( 0, -50, 0, -60,QPen(QPen::darkBlue,2)));
77  Lines.append(new Line( 0, 50, 0, 60,QPen(QPen::darkBlue,2)));
78 
79  Arcs.append(new Arc( -5,-50, 10, 10, 0, 16*360, QPen(QPen::darkBlue,2)));
80  Arcs.append(new Arc( -5, 40, 10, 10, 0, 16*360, QPen(QPen::darkBlue,2)));
81 
82  Texts.append(new Text(-25,-32, "D", QPen::darkBlue, 12.0));
83  Texts.append(new Text( 11,-32, "Q", QPen::darkBlue, 12.0));
84  Texts.append(new Text( -5,-39, "S", QPen::darkBlue, 12.0));
85  Texts.append(new Text( 11, 7, "Q", QPen::darkBlue, 12.0));
86  Texts.current()->over=true;
87  Texts.append(new Text( -5, 17, "R", QPen::darkBlue, 12.0));
88 
89  Ports.append(new Port(0, -60)); // S
90  Ports.append(new Port(-50,-20)); // D
91  Ports.append(new Port(-50, 20)); // CLK
92  Ports.append(new Port( 0, 60)); // R
93  Ports.append(new Port( 50, 20)); // QB
94  Ports.append(new Port( 50,-20)); // Q
95 
96  x1 = -50; y1 = -60;
97  x2 = 50; y2 = 60;
98 }
99 
100 QString dff_SR::vhdlCode( int )
101 {
102  QString s="";
103 
104  QString td = Props.at(2)->Value; // delay time
105  if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format
106  td += ";\n";
107 
108  QString S = Ports.at(0)->Connection->Name;
109  QString D = Ports.at(1)->Connection->Name;
110  QString CLK = Ports.at(2)->Connection->Name;
111  QString R = Ports.at(3)->Connection->Name;
112  QString QB = Ports.at(4)->Connection->Name;
113  QString Q = Ports.at(5)->Connection->Name;
114 
115  s = "\n "+Name+":process ("+S+", "+CLK+", "+R+") is\n"+
116  " variable state : std_logic;\n"+
117  " begin\n" +
118  " if ("+S+" = '0') then\n"+
119  " state := '1';\n"+
120  " elsif ("+R+" = '0') then\n"+
121  " state := '0';\n"+
122  " elsif ("+CLK+" = '1' and "+CLK+"'event) then\n"+
123  " state := "+D+";\n"+
124  " end if;\n"+
125  " "+Q+" <= state"+td+
126  " "+QB+" <= not state"+td+
127  " end process;\n";
128  return s;
129 }
130 
131 QString dff_SR::verilogCode( int )
132 {
133  QString td = Props.at(2)->Value; // delay time
134  if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
135 
136  QString l = "";
137 
138  QString S = Ports.at(0)->Connection->Name;
139  QString D = Ports.at(1)->Connection->Name;
140  QString CLK = Ports.at(2)->Connection->Name;
141  QString R = Ports.at(3)->Connection->Name;
142  QString QB = Ports.at(4)->Connection->Name;
143  QString Q = Ports.at(5)->Connection->Name;
144 
145  QString QR = "Q_reg" + Name + Q;
146  QString QBR = "QB_reg" + Name + QB;
147  QString ST = "Q_state" + Name;
148 
149  l = "\n // "+Name+" d flip-flop with set and reset\n"+
150  " assign "+Q+" = "+QR+";\n"+
151  " reg "+QR+" = 0;\n"+
152  " assign "+QB+" = "+QBR+";\n"+
153  " reg "+QBR+" = 1;\n"+
154  " reg "+ST+" = 0;\n"+
155  " always @ (posedge "+CLK+")\n"+
156  " begin\n"+
157  " if ("+R+" == 1 && "+S+" == 1)\n"+
158  " begin\n"+
159  " "+ST+" = "+D+";\n"+
160  " "+QR+" <="+td+" "+ST+";\n"+
161  " "+QBR+" <="+td+" ~"+ST+";\n"+
162  " end\n"+
163  " end\n"+
164  " always @ ("+R+")\n"+
165  " begin\n"+
166  " if ("+R+" == 0) "+ST+" = 0;\n"+
167  " "+QR+" <="+td+" "+ST+";\n"+
168  " "+QBR+" <="+td+" ~"+ST+";\n"+
169  " end\n"+
170  " always @ ("+S+")\n"+
171  " begin if ("+S+" == 0) "+ST+" = 1;\n"+
172  " "+QR+" <="+td+" "+ST+";\n"+
173  " "+QBR+" <="+td+" ~"+ST+";\n"+
174  " end\n";
175  return l;
176 }
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