Conclusions The problems of phase 1 below were due to running the xkit -t xh018 script from a directory that already contained entries resulting from another technology. That confused it well and good. Phase 1 Research Links How to use PDK in cadence Cadence getting started see below: What […]
Research Links Simple inverter layout Chapter 5 Virtuoso Layout Editor Cadence Tutorial for Cadence version 6.1 Inkwon Hwang Feb, 2010
I had a problem where when I returned to my opensuse based machine my Cadence design library was no where to be seen in the library manager. In order to for it to show up again in the list there are 2 ways of approaching the problem. With the Log […]
On a box connected on the same local network – ssh -Y -l username IP address The -Y switch enables trusted forwarding of X Window applications from the host computer so that they can run in the X Window environment of the client computer. The -l switch allows you to […]
Research Links Mza's notes on Cadence Cadence Virtuoso SetUp Guide
Research Links Install Cadence 6.1 on Ubuntu 10.04 Google Search: install "cadence" virtuoso ubuntu Design Kit Information Setup IBM 180nM design kit Instructions: SetUp Design Kit Google: cadence virtuoso how to install design kit IBM 180nM 7RF Process Overview Ancillary Links Cadence Tutorial North Dakota University Notes Cadence […]
If you need a voltage reference when doing energy harvesting it is very helpful have a band gap reference that uses very little current. Â This topology uses “Self Cascode Mosfet” Â abreviated as SCM. Â The LTSPICE design uses 4.5 nano Amperes and outputs a 0.6 Volt reference voltage. Research Links REFERENCIA-DE-CORRENTE-CMOS-PARA-APLICACOES-DE-ULTRABAIXO-CONSUMO-DE-POTENCIAÂ […]
Jacob Baker maintains CMOSedu.com. There is a large amount of useful material there. Research Links CMOS Circuit Design, Layout, and Simulation, Third Edition – there are files on that page for use with LTSPICE , Cadence etc Setting up ELECTRIC to work with LTSPICE VLSI and ASIC Technology Standard Cell […]
See the resulting project report here: 1.2V Supply voltage Band gap reference in 180nm IBM process Band Gap Reference – Papers CMOS Bandgap Voltage Reference With 1.8-V Power Supply DESIGN OF A CMOS BANDGAP REFERENCE WITH LOWTEMPERATURE COEFFICIENT AND HIGH POWER SUPPLY REJECTION PERFORMANCE BandGap Reference Design in SubMicron CMOS Technology LOW-VOLTAGE […]
Level 8 MOSFET models for the PMOS and NMOS FETs in the CD4007 mosfet array chip courtesy of Dr Lynn Fuller of R.I.T. LTSpice Schematic file – All the model parameters are included as spice directives on the schematic so this should be portable and run right out of the box […]