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Consider 5 different processors listed below, executing the same instruction set with the clock rates and cycles per instruction given in the following table:

 Choose the one that has the best performance.

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What is the logic equation for the circuit below? The "!" symbol must be considered as negation indicator.

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Considering the figure below, t1, t2, t3 and t4 correspond, respectively, to wich timing characteristics? 

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Wich structure dies the code below implements?

---------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------

entity example is

port(	I:	in std_logic;
	clock:	in std_logic;
	load:	in std_logic;
	clear:	in std_logic;
	Q:	out std_logic
);
end example;

----------------------------------------------------

architecture behv of example is

    signal Q_tmp: std_logic;

begin

    process(I, clock, load, clear)
    begin

	if clear = '0' then

            Q_tmp <= '0';

	elsif (clock='1' and clock'event) then

	    if load = '1' then

		Q_tmp <= I;

	    end if;
	end if;

    end process;

    Q <= Q_tmp;

end behv;

---------------------------------------------------
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What logic gate does the CMOS layout below represents?

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Wich logic gate does the circuit below implement?

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In a Moore type finite state machine, the output signals depend on __________________.

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What does the circuit below implement?

 

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Considering that E1, E2 and E3 are input signals and S is an output signal, the waveforms below represent the behavior of a/an ______________ logic gate.

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In Object-Oriented Programming (OOP) the term class means to a set of:

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The Karnaugh's map shown below corresponds to the following logic function: _____________________ (being '!' the negation of the variable).



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The function below can be used to calculate _____________.

 

int x(int in) {

int i;

for (i=2;i<in;i++) {

if (in == i*i) {

return i;

};

};

return 0;

};

 

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The logical equation (S = a + b + c) corresponds to a:

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The device depicted below is a __________ transistor.



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What does the code below implement?

 

module x(out,data1,data2,op);

    input [2:0] op;

    input [3:0] data1,data2;

    output reg [3:0] out;

 

  always @(op or data1 or data2)

  case (op)

    3'b001: out = data1 | data2;

    3'b010 : out= data1 ^ data2;

    3'b101 : out = ~data1;

    default : out = 4'b0;

   endcase

endmodule

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